Hi, I’m Yuchen Zhu, currently a Ph.D. student in Computer Science at Northwestern University, a member of PARAG@N advised by Prof. Nikos Hardavellas.
My primary research focus is to provide architectural support for next-gen quantum computers. Concretely, my research interests include circuit design, circuit compilation, and pulse-level control for quantum computer systems.
I am always looking for collaborations and internship opportunities. Please feel free to drop me an email.
In the scaling development of quantum computers, the calibration process emerges as a critical challenge. Existing calibration methods, utilizing the same pulse waveform for two-qubit gates across the device, overlook hardware differences among physical qubits and lack efficient parallel calibration. In this paper, we enlarge the pulse candidates for two-qubit gates to three pulse waveforms, and introduce a fine-grained calibration protocol. In the calibration protocol, three policies are proposed to profile each qubit pair with its optimal pulse waveform. Afterwards, calibration subgraphs are introduced to enable parallel calibraton through identifying compatible calibration operations. The protocol is validated on real machine with up to 127 qubits. Real-machine experiments demonstrates a minimum gate error of 0.001 with a median error of 0.006 which is 1.84x reduction compared to default pulse waveform provided by IBM. On device level, a double fold increase in quantum volume as well as 2.3x reduction in error per layered gate are achieved. The proposed protocol leverages the potential current hardware and could server as an important step toward fault-tolerant quantum computing.
@inproceedings{zhu2024leveraginghardwarepoweroptimal,title={Leveraging Hardware Power through Optimal Pulse Profiling for Each Qubit Pair},author={Zhu, Yuchen and Cheng, Jinglei and Li, Boxi and Zhou, Yidong and Ding, Yufei and Liang, Zhiding},booktitle={2025 52nd International Symposium on Computer Architecture (ISCA)},year={2025},eprint={2411.19308},archiveprefix={arXiv},primaryclass={quant-ph},url={https://arxiv.org/abs/2411.19308},}
EPOC: A Novel Pulse Generation Framework Incorporating Advanced Synthesis Techniques for Quantum Circuits
Jinglei Cheng, Yuchen Zhu, Yidong Zhou, and 3 more authors
In 2025 62nd ACM/IEEE Design Automation Conference (DAC), 2025
In this paper we propose EPOC, an efficient pulse generation framework for quantum circuits that combines ZX-Calculus, circuit partitioning, and circuit synthesis to accelerate pulse generation. Unlike previous works that focus on generating pulses from unitary matrices without exploring equivalent representations, EPOC employs a finer granularity approach by grouping quantum gates and decomposing the resulting unitary matrices into smaller ones using synthesis techniques. This enables increased parallelism and decreased latency in quantum pulses. EPOC also continuously optimizes the circuit by identifying equivalent representations, leading to further reductions in circuit latency while minimizing the computational overhead associated with quantum optimal control. We introduce circuit synthesis into the workflow of quantum optimal control for the first time and achieve a 31.74% reduction in latency compared to previous work and a 76.80% reduction compared to the gate-based method for creating pulses. The approach demonstrates the potential for significant performance improvements in quantum circuits while minimizing computational overhead.
@inproceedings{cheng2024epoc,title={EPOC: A Novel Pulse Generation Framework Incorporating Advanced Synthesis Techniques for Quantum Circuits},author={Cheng, Jinglei and Zhu, Yuchen and Zhou, Yidong and Ren, Hang and Song, Zhixin and Liang, Zhiding},booktitle={2025 62nd ACM/IEEE Design Automation Conference (DAC)},journal={arXiv preprint arXiv:2405.03804},year={2025},}
